![]() ![]() We have developed a spread-spectrum Phase-Locked Loop (PLL) for serial Advanced Technology Attachment (ATA) applications. The peak-to-peak jitter at 6GHz output of non spread-spectrum is 6.16ps, and the EMI reduction is 22.49dB with 5000ppm down spread to 5.97GHz. The chip is designed in TSMC 0.18um 1P6M CMOS process with active area of 500um×300um, and the simulation results consumes 60.43mW with 1.8V supply. In addition, a multi-stage-noise-shaping (MASH) delta-sigma modulator (ΔΣ modulator) is used to reduce fractional spurs and quantization error for high EMI reduction. This research propose a SSCG using a ring voltage-controlled oscillators (Ring-VCO) at 6GHz operating frequency By using the proposed Ring-VCO, the active area of SSCG is 65% of comparable LC tank implementations, and Ring-VCO is much easier to characterized for any CMOS process. However, the monolithic inductors always occupy a large area, and required precisely characteristic for different fabrication processes. Conventional methods use inductor-capacitance (LC) tank to fulfill the high frequency requirement for SATA-3.0. #Clockgen pll download generator#In this paper, a small area spread-spectrum clock generator (SSCG) with high EMI reduction for SATA-3.0 is presented. ![]()
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